{"id":13960,"date":"2014-12-16T08:57:00","date_gmt":"2014-12-16T07:57:00","guid":{"rendered":"https:\/\/rafen.app\/uncategorized\/design-and-verification-of-hardware\/"},"modified":"2014-12-16T08:57:00","modified_gmt":"2014-12-16T07:57:00","slug":"design-and-verification-of-hardware","status":"publish","type":"post","link":"https:\/\/raf.edu.rs\/en\/subjects\/design-and-verification-of-hardware\/","title":{"rendered":"Design and verification of hardware"},"content":{"rendered":"<p><span >Introduction to the formal specification and verification of hardware: the context, design of circuits, errors and cycle of design. Formal verification, simulations, test vectors, test-benches, design-for-test and design-for-verification styles of writing code and verification based on assertion (assertion-based verification, ABV). Formal (static), semi-formal and informal (dynamic, functional) approach to verification. Hardware verification languages (HVLs). Properties specification languages (PSLs). Formal properties of hardware description languages (FPLs). Symbolic model checking, golden design, logical equivalence. Approaches to verification based on Boolean functions. Representations of Boolean functions using binary decision diagrams (BDD). Extensions and variants of BDDs. Approaches to verification based on the satisfiability problem (SAT), limited model checking (BMC), symbolic trajectory estimation (STE), solvers of SAT problems, combined SAT-BDD checkers. Approaches to verification based on finite state machines (FSM). The formal verification of hardware in higher order logic (PTL, CTL, LTL). Descriptions of hardware using temporal structures, logical formulas and specifications. Probabilistic model checking.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Introduction to the formal specification and verification of hardware: the context, design of circuits, errors and cycle of design. Formal verification, simulations, test vectors, test-benches, design-for-test and design-for-verification styles of writing code and verification based &#8230; <a title=\"Design and verification of hardware\" class=\"read-more\" href=\"https:\/\/raf.edu.rs\/en\/subjects\/design-and-verification-of-hardware\/\" aria-label=\"More on Design and verification of hardware\">Read more<\/a><\/p>\n <a href=\"https:\/\/raf.edu.rs\/en\/subjects\/design-and-verification-of-hardware\/\" class=\"more-link\" title=\"Read more\">Read more<\/a>","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[199],"tags":[],"class_list":["post-13960","post","type-post","status-publish","format-standard","hentry","category-subjects"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.7 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Design and verification of hardware - School of Computing<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/raf.edu.rs\/en\/subjects\/design-and-verification-of-hardware\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Design and verification of hardware - School of Computing\" \/>\n<meta property=\"og:description\" content=\"Introduction to the formal specification and verification of hardware: the context, design of circuits, errors and cycle of design. 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