{"id":14004,"date":"2021-02-10T13:45:00","date_gmt":"2021-02-10T12:45:00","guid":{"rendered":"https:\/\/rafen.app\/uncategorized\/design-and-verification\/"},"modified":"2021-02-10T13:45:00","modified_gmt":"2021-02-10T12:45:00","slug":"design-and-verification","status":"publish","type":"post","link":"https:\/\/raf.edu.rs\/en\/subjects\/design-and-verification\/","title":{"rendered":"Design and Verification"},"content":{"rendered":"
Objectives and outcomes<\/h5>\n

Acquisition and systematization of knowledge related to the functional verification of integrated circuits,
\nfrom verification at the module and block level, to system verification. Acquiring competence for
\nfunctional block-level verification. Students gain the competence in using software tools for verification
\n(SystemVerilog), creating a verification plan, defining a verification environment and verifying a simple
\nblock or component.<\/p>\n

<\/p>\n

Lectures<\/h5>\n

Basics of Verilog language. Basic elements of the SystemVerilog language. SystemVerilog language
\nparadigms – object oriented and declarative paradigm. The notion of time in SystemVerilog. Events –
\ndefinition and use. Ordinary and time-consuming methods. Inheritance. Basic verification concepts:
\norganization and import of files, linking the environment with the design, design simulation, execution
\nsteps, parts of the verification environment: driver, monitor, checker. Advanced features of the
\nSystemVerilog language: ports, pointers, messages, coverage. Block level verification and system level
\nverification. Fundamentals of UVM methodology.<\/p>\n

<\/p>\n

Practical classes<\/h5>\n

Students deepen the knowledge acquired in lectures by acquiring the skill of realizing the verification
\nenvironment with the application of the professional system SystemVerilog.<\/p>\n