Objectives and outcomes
Acquisition and systematization of knowledge related to the functional verification of integrated circuits,
from verification at the module and block level, to system verification. Acquiring competence for
functional block-level verification. Students gain the competence in using software tools for verification
(SystemVerilog), creating a verification plan, defining a verification environment and verifying a simple
block or component.
Lectures
Basics of Verilog language. Basic elements of the SystemVerilog language. SystemVerilog language
paradigms – object oriented and declarative paradigm. The notion of time in SystemVerilog. Events –
definition and use. Ordinary and time-consuming methods. Inheritance. Basic verification concepts:
organization and import of files, linking the environment with the design, design simulation, execution
steps, parts of the verification environment: driver, monitor, checker. Advanced features of the
SystemVerilog language: ports, pointers, messages, coverage. Block level verification and system level
verification. Fundamentals of UVM methodology.
Practical classes
Students deepen the knowledge acquired in lectures by acquiring the skill of realizing the verification
environment with the application of the professional system SystemVerilog.
- The basics of the UNIX environment necessary for using verification tools.
- Basics of Verilog language and simulation.
- SystemVerilog language – data types, classes, methods, events.
- Introduction to verification methodology.
- Block verification.